Tags¶
DDR4¶
- DDR4 Tutorial - Understanding the Basics
- DDR4 SDRAM - Initialization, Training and Calibration
- DDR4 SDRAM - Timing Parameters Cheat Sheet
- DDR4 SDRAM - Understanding Timing Parameters
Formal Verification¶
- A Blueprint for Formal Verification
- A Gentle Introduction to Formal Verification
- SystemVerilog Assertions Basics
Memory¶
- DDR4 Tutorial - Understanding the Basics
- DDR4 SDRAM - Initialization, Training and Calibration
- DDR4 SDRAM - Timing Parameters Cheat Sheet
- DDR4 SDRAM - Understanding Timing Parameters
OCP¶
Synopsys¶
System Design¶
SystemVerilog¶
- SystemVerilog Enum
- SystemVerilog Generate Construct
- SystemVerilog Macros
- SystemVerilog Random Stability
- SystemVerilog Randomization & Random Number Generation
- Splitting and extracting specific modules from VPD or VCD dump
- SystemVerilog Style Guide
- SystemVerilog Assertions Basics
- SystemVerilog Associative Arrays
- SystemVerilog Casting
- SystemVerilog convert hex, int, binary data type to string
- SystemVerilog convert string to hex, int, binary data type
- SystemVerilog Dynamic Arrays
- SystemVerilog Queues
- Methods and utilities to manipulate SystemVerilog strings
- 10 SystemVerilog Utilities You Must Know
- UVM field macros
- How to Create & Use VMC (SWIFT) Models
