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This site is dedicated to all aspects of hardware development, including the core concepts behind ASIC/SoC Design and Verification, Board and System Design, and the dynamics behind engineering culture.

If you're new, start with the popular section right below. Further down, you will see all articles categorized by topic. Enjoy!


Explore By Topic

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ASIC/SoC Design

DDR4 Tutorial - Understanding the Basics
An in-depth look at the fundamentals of DDR Memory

DDR4 - Initialization, Training and ZQ Calibration
Understanding DRAM Initialization, ZQCL, Read/Write training, Vref Calibration and much more

DDR4 - Understanding Timing Parameters
A tutorial on DDR4 timing parameters

DDR4 - Timing Parameters Cheat Sheet
A quick reference for timing parameters

System Design

Modular Design in the Open Compute Project
A study of system design in the Open Compute Project

Facebook and the Open Compute Project
A detailed look at Facebook's server - Yosemite

HP Moonshot Dissection
Detailed study of the HP moonshot chassis

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Formal Verification

SystemVerilog Assertions Basics
A tutorial on SVA, assertion types, |->, |=>, cover property, with tons of examples

A Gentle Introduction to Formal Verification
What is Formal, When to use Formal, Formal vs Functional Verification

A Blueprint for Formal Verification
Get your hands dirty with your first FV testbench. Also includes a path to signing off with Formal.

SystemVerilog Language & UVM

SystemVerilog Generate Construct
A detailed look at how to use generate in loops, conditions and assertions

SystemVerilog Macros
How to write macros, what do those `, ``, `" mean

SystemVerilog Randomization & Random Number Generation
$random, $urandom, $urandom_range, randomize, std::randomize

SystemVerilog Random Stability
Deep dive into Random Stability, Rand State and how to recreat failed tests

Style Guide for SystemVerilog Code
Inspired by Python PEP8, this is the missing Styleguide for SystemVerilog. Make code beautiful again.

10 Useful SystemVerilog Utilities
`__FILE__, `__LINE__, $countbits, $size and more ...

How to Create & Use VMC SWIFT Models
How to securely distribute IP simulation models


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