1. DDR4 SDRAM - Understanding the Basics
Physical Structure, READ, WRITE, ACTIVATE, ...

2. DDR4 SDRAM - Initialization, Training and ZQ Calibration
DRAM Initialization, ZQCL, Read/Write training, ...

3. DDR4 SDRAM - Understanding Timing Parameters
CL, CWL, tCCD_S/tCCD_L, tDQSS, etc ...

4. DDR4 SDRAM - Timing Parameters Cheat Sheet
A quick reference ...

1. SystemVerilog Assertions Basics
Assertion types, |-> |=>, cover property, examples ...

2. A Gentle Introduction to Formal Verification
What is Formal, When to use Formal, Formal vs Functional Verification ...

3. A Blueprint for Formal Verification
Path to signing off with Formal ...

1. SystemVerilog Generate Construct
Using generate in loops, conditions and assertions

2. SystemVerilog Macros, backtick (`), double-backtick (``)
How to write macros, what do those `, `` & `" mean

3. SystemVerilog Randomization & Random Number Generation
$random, $urandom, $urandom_range, randomize, std::randomize ...

4. SystemVerilog Random Stability
Random Stability, Rand State, Recreating failed tests ...

5. Style Guide for SystemVerilog Code
Make code beautiful again ...

6. How to Create & Use VMC SWIFT Models
Securely distributing IP simulation models ...

7. 10 SystemVerilog Utilities
`__FILE__, `__LINE__, $countbits, $size and more ...