/* systemverilog.io */


Welcome to systemverilog.io!

While the hardware engineering and chip design community is small compared to that of software engineering, there's definitely something to be learnt from software's wonderful world of countless open-source libraries and frameworks, and their vibrant online community that calls and responds to each other's questions with commendable enthusiasm.

SystemVerilog and hardware engineering does have its heroes too - from Cliff Cummings' Sunburst Design Papers and John Cooley's DeepChip newsletters to a budding community on StackOverflow. But I think there is room for sharing quality instruction, knowledge, experiences and code. To that effect, this website attempts to be another resource to help understand and apply SystemVerilog and its various quirks and nuances. Its beginnings will be modest, the plan is to approach each concept piecemeal, explore it in depth and provide working code with all the explanation. With time I wish to make this site a good repository of SystemVerilog resources.

A lot of thought was put into designing the layout of this website to make it attractive and conducive for learning and reading code. I hope you enjoy what you read here and find it useful.


Please enter your email address if you would like to be notified when a new article is published ... I promise you won't be spammed.


Systemverilog.io is a static website that uses the lovely Mozilla Nunjucks templating engine. The base CSS used is Bootstrap3. Fonts used are Inconsolata, Merriweather and Droid Sans Mono. All icons are from the one-and-only FontAwesome library.

The final HTML, minified CSS & JS are generated using Grunt along with a few essential grunt-contrib-* and grunt-nunjucks-2-html packages. The build artifacts are deployed on Firebase and the website source files are stored in a private Bitbucket repository. The code examples written for the articles are checked into a separate repository on Github.

My editor of choice for web development is SublimeText3 and for SystemVerilog it is Vim.


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