When a device with a DRAM sub-system is powered up, a number of things happen before the DRAM gets to an operational state. The following state-machine from the JEDEC specification shows the various states the DRAM transitions through from power-up.
In essence, the initialization procedure consists of 4 distinct phases
To better understand the following sections, let's assume you have a system which looks like this - An ASIC/FPGA/Processor with 1 DIMM module.
Power-up and initialization is a fixed well-defined sequence of steps. Typically, when the system is powered up and the controller in the ASIC/FPGA/Processor is removed out of reset, it automatically performs the power-up and initialization sequence. Here's a super-simplified version of what the controller does. For exact details refer to section 3.3 in the JESD79-49A specification.
RESETand activate ClockEnable
MRScommands and load the Mode Registers [The mode registers are loaded in a specific sequence]
At this point the DRAMs on the DIMM module understand what frequency they have to operate at, what the
CAS Latency (CL),
CAS Write Latency (CWL) and few other timing parameters are.
Check out the article on DDR4 timing parameters to learn more about CL, CWL, etc ...
ZQ Calibration is related to the data pins [DQ]. To understand what ZQ calibration does and why it is required, we need to first look at the circuit behind each DQ pin. Remember, the DQ pin is bidirectional. It is responsible for sending data back during reads and receiving data during writes.
Now, if you look within a DRAM, the circuit behind every DQ pin is made up of a set of parallel 240Ω resistor legs, as shown in Figure 4. Because of the nature of CMOS devices, these resistors are never exactly 240Ω. The resistance is even affected due to voltage and temperature changes. So, they are made tunable.
In order to tune these resistors to exactly 240Ω, each DRAM has
DQ calibration control blockand
ZQpin to which an external
precision (+/- 1%) 240Ωresistor is connected.
This external precision resistor is the "reference" and it remains at 240Ω at all temperatures. When a
ZQCL command is issued during initialization, this DQ calibration control block gets enabled and it produces a tuning value. This value is then copied over to each DQ's internal circuitry.
Ok, the above explanation is a quick overview of ZQ calibration. If you're satisfied, proceed to the next section. If you're itching for more details, read on.
The 240Ω resistor leg within a DQ circuit is a type of resistor called "Poly Silicon Resistor" and is, typically, slightly larger than 240Ω (Poly silicon resistor is a type of resistor that is compatible with CMOS technology). There are number of p-channel devices that are connected in parallel to this poly-resistor so that it can be tuned exactly to 240Ω.
The figure below zooms into one 240Ω leg of the DQ circuit and shows 5 p-channel devices connected to the poly-resistor. These little transistors are set based on input
Now, the circuit connected to the DQ calibration control block is essentially a resistor divider circuit with one of the resistors being the poly and the other is the precision 240Ω. When a
ZQCL command is issued during initialization, this DQ calibration control block is enabled and an internal comparator within the DQ calibration control block tunes the p-channel devices using
VOH[0:4] until the voltage is exactly
VDDq/2 (A classic resistor divider). At this point the calibration has been complete and the
VOH values are transferred all the DQ pins.
Next, you may wonder why the DQ pins even have this parallel network of 240Ω resistors in the first place!
Having a bank of parallel 240Ω resistors allows you to tune the drive strength (for READs) and termination resistance (for WRITEs). Every PCB layout is different so this tuning capability is required to improve signal integrity, maximize the signal's eye-size and allow the DRAM to operate at high-speeds.
The signal drive strength from the DRAM can be controlled by setting mode register MR1[2:1]. The termination can be controlled using a combination of
RTT_NOM, RTT_WR & RTT_PARK in mode registers MR1, 2 & 5 respectively.
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In DDR4 the termination style of the data lines [
DQ] was changed from CTT (Center Tapped Termination, also called SSTL Series-Stud Terminated Logic) to POD (Pseudo Open Drain). This was done to improve signal integrity at high speeds and to save IO power. This is not the first of its kind, GDDR5 (the graphics DRAM) uses POD as well.
What this means is, in DDR3
Vdd/2 is used as the voltage reference to decide if the [
DQ] signal is
1. Take another look at the left-hand side of Figure 8, the receiver is essentially a voltage divider circuit.
But in DDR4 there is no voltage divider circuit at the receiver. It instead has an internal voltage reference which it uses to decide if the signal on data lines [
1. This voltage reference is called
VrefDQ can be set using mode registers MR6 and it needs to be set correctly by the memory controller during the VrefDQ calibration phase.
At this point the initialization procedure is complete and the DRAMs are in
IDLE state, but the memory is STILL not operational. The Controller and PHY have to perform a few more important steps before data can be reliably written-to or read-from the DRAM. This important phase is called Read/Write Training (or Memory Training or Initial Calibration) wherein the controller (or PHY)
CK] and data strobe [
DQS] at the DRAM
This section is about the following circle in the state machine
Let's take a closer look at our example system. The picture below shows how the data signals and address/commmand signals are connected between the ASIC/Processor and the DRAMs on the DIMM.
[DQ & DQS]are connected to each memory in a star topology because each memory is connected to a different portion of the 72 data lines
[A, CK, CKE, WE, CSn]on a DIMM are connected using a technique called fly-by routing topology. This is done because all DRAMs on the DIMM share the same address lines and fly-by routing is required to achieve better signal integrity and the high speeds.
So, from the ASIC/Processor's point of view each DRAM memory on the DIMM is located at a different distance. Or from the DIMM's point of view, the skew between clock and data is different for each DRAM on the DIMM.
The DRAM is a fairly dumb device. Say you intend to do a
WRITE operation, during initialization you tell the DRAM what the
CAS Write Latency is by programming one of its Mode Registers (CWL is the time delay between the column address and data at the inputs of a DRAM), and you have to honor this timing parameter at all times. The memory controller needs to account for the board trace delays and the fly-by routing delays and launch Address and Data with the correct skew between them so that the Address and Data arrive at the memory with
CWL latency between them.
For example, if you program the
CAS Write Latency to
9, once the ASIC/uP launches the Column Address, it will need to launch the different data bits at different times so that they all arrive at the DRAMs at a
Something similar to the above needs to be done for
READs as well. Since each DRAM on the DIMM is located at a different distance, when a
READ is issued each DRAM on the DIMM will see the
READ command at different times and subsequently the data from each DRAM arrives at the ASIC/Processor at different times. During Initial Calibration, the ASIC/Processor figures out what the delays from each of the DRAMs are and trains its internal circuitry accordingly so that it latches the data from the various DRAMs at the right moment.
For Read/Write Training, the Controller/PHY IPs typically offer a number of algorithms. The most common ones are:
MPR Pattern Write
All the above algorithms are performed by the memory controller and usually require you to only enable/disable each algorithm through a register and take action in case failures are reported. The following sections go into more detail about what the controller does when you enable each of these algorithms.
When writing to a DRAM an important timing parameter that cannot be violated is tDQSS. tDQSS is the position of the DataStrobe (DQS) relative to Clock (CK). tDQSS has to be within a tDQSS(MIN) and tDQSS(MAX) as defined in the spec. If tDQSS is violated and falls outside the range, wrong data may be written to the memory.
Since the Clock to Data/DataStrobe skew is different for each DRAM on the DIMM, the memory controller needs to train itself so that it can compensate for this skew and maintain tDQSS at the input of each DRAM on the DIMM.
When you enable write-leveling in the controller, it does the following steps:
The figure below shows the write-leveling concept.
MPR (Multi Purpose Register) Pattern Write isn't exactly a calibration algorithm. It is typically a step that is performed before Read Centering and Write Centering.
DDR4 DRAMs contain four 8-bit programmable registers called MPR registers that are used for DQ bit training (i.e., Read and Write Centering). MPR access mode is enabled by setting Mode Register MR3 = 1. When this mode is enabled READs and WRITEs issued to the DRAM are diverted to the Multi Purpose Register instead of the memory banks.
The purpose of read centering is to train the internal read capture circuitry in the controller (or PHY) to capture the data in the center of the data eye. The memory controller (or PHY)
Similar to the read centering step, the purpose of write centering is to set the write delay for each data bit so that write data is centered on the corresponding write strobe edge at the DRAM device.
During write centering the PHY does the following
WRITE-READ-SHIFT-COMPARE loop continuously
From the above loop the PHY can determine for what write-delay range it reads back good data, and hence it can figure out the left and write edges of the write-data eye. Using this dat,a the DQ is centered to the DQS for writes.
In a device such as a network switch or router, there could be changes in Voltage and Temperature during its course of operation. To keep the signal integrity and data access reliable, some of the parameters that were trained during initialization and read/write training have to be re-run. Memory controller and PHY IPs typically provide the following two periodic calibration processes.
Periodic ZQ- Also known as ZQ Calibration Short (ZQCS). It is used to run ZQ calibration periodically to tune the 240Ω resistor that was described earlier.
Periodic Read Centering- To re-calculate read delays and other read related parameters
Enabling periodic calibration is optional because if you know your device will be deployed in stable temperature conditions, then the initial ZQ calibration and read/write training is sufficient.
Typically, the memory controller or PHY allow you to set a timer and enable periodic calibration through their registers. Once the timer is set, periodic calibration is run every time the timer expires.
There are 4 steps to be completed before the DRAM can be used
Once this is done system is officially in IDLE and operational. You may need to enable periodic calibration depending upon the conditions in which your device is deployed.