DDR4 SDRAMs are very prevalent in devices that use ASICs and FPGAs. In this article we explore the basics.
A good place to start is to look at some of the essential IOs and understand what their functions are. From there we'll dive deeper until we get to the basic unit that makes up a DRAM memory.
As you would expect, the DRAM has clock, reset, chip-select, address and data inputs. The table below has little more detail about each of them. This is not a complete list of IOs, only the basic ones are listed here. Take a little time to carefully read what each IO does, especially the dual-function address inputs.
|RESET_n||Input||DRAM is active only when this signal is HIGH|
|CS_n||Input||The memory looks at all the other inputs only if this is LOW.|
|CKE||Input||Clock Enable. HIGH activates internal clock signals and device input buffers and output drivers.|
|CK_t/CK_c||Input||Differential clock inputs. All address & control signals are sampled at the crossing of posedge of CK_t & negedge of CK_n.|
|DQ/DQS||Inout||Data Bus & Data Strobe. This is how data is written in and read out. The strobe is essentially a data valid flag.|
|Input||These are dual function inputs. When ACT_n & CS_n are LOW, these are interpreted as Row Address Bits. When ACT_n is HIGH, these are interpreted as command pins to indicate READ, WRITE or other commands.|
|ACT_n||Input||Activate command input|
|Input||Bank Group, Bank Address|
The top-level picture shows what a DRAM looks like on the outside. Going a level deeper, this is how memory is organized - in Bank Groups and Banks.
READ from memory you provide an address and to
WRITE to it you additionally provide data. This address provided by you, the user, is typically called "logical address". This logical address is translated to a physical address before it is presented to the DRAM. The physical address is made up of the following fields:
these individual fields are then used to identify the exact location in the memory to read-from or write-to.
Going down another level, this is what you'll see within each Bank.
Once the Bank Group and Bank have been identified, the Row part of the address activates a line in the memory array. This is called the "Word Line" and activating it reads data from the memory array into something called "Sense Amplifiers". The Column address then reads out a part of the word that was loaded into the Sense Amps. The width of the column is called the "Bit Line".
The width of a colum is standard - it is either 4 bits, 8 bits or 16 bits wide and DRAMs are classified as
x4, x8 or x16 based on this column width. Another thing to note is that, the width of
DQ data bus is same as the column width. So, to simplify things, you can say that DRAMs are classified based on the width of the
x16 devices have only 2 Bank Groups whereas
x8 have 4 as shown in figure 2.]
Analogy Time: A DRAM chip is equivalent to a building full of file cabinets
Bank Group Identifies the floor
Bank Address Identifies the file cabinet within that floor where the file you need is located
Row Address Identifies which drawer in the cabinet the file is located. Reading data into the Sense Amplifiers is equivalent to opening/pulling out the file drawer.
Col Address Identifies the file number within this drawer
At the lowest level, a bit is essentially a capacitor that holds the charge and a transistor acting as a switch.
Since the capacitor discharges over time, the information eventually fades unless the capacitor is periodically
REFRESHed. This is where the 'D' in DRAM comes from - it refers to Dynamic as opposed to SRAM (Static Random Access Memory).
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DRAMs come in standard sizes and this is specified in the JEDEC spec. JEDEC is the standards committee that decides the design and roadmap of DDR memories. This is from section 2.7 of the DDR4 JEDEC specification (JESD79-4B).
Let's try to make some more sense of the above table by hand-calculating two of the sizes
/* 4Gb x4 Device */ Number of Row Address bits: A0-A15 = 16 bits Total number of row = 2^16 = 64K Number of Column Address bits: A0-A9 = 10 bits Number of columns per row = 1K Width of each column = 4 bits Number of Bank Groups = 4 Number of Banks = 4 Total DRAM Capacity = Num.Rows x Num.Columns x Width.of.Column x Num.BankGroups x Num.Banks Total DRAM Capacity = 64K x 1K x 4 x 4 x 4 = 4Gb/* 4Gb x8 Device */ Number of Row Address bits: A0-A154 = 15 bits Total number of row = 2^15 = 32K Number of Column Address bits: A0-A9 = 10 bits Number of columns per row = 1K Width of each column = 8 bits Number of Bank Groups = 4 Number of Banks = 4 Total DRAM Capacity = Num.Rows x Num.Columns x Width.of.Column x Num.BankGroups x Num.Banks Total DRAM Capacity = 32K x 1K x 8 x 4 x 4 = 4Gb
In the table above, there's a mention of
Page Size. Page size is essentially the number of bits per row. Or put it another way, it is the number of bits loaded into the Sense Amps when a row is activated. Since the column address is 10 bits wide, there are 1K bit-lines per row. So, for a x4 device number of bits is 1K x 4 = 4K bits (or 512B). Similarly, for x8 device it is 1KB and for x16 it is 2KB per page.
When dealing with DRAMs you'll come across terminology such as Single-Rank, Dual-Rank or Quad-Rank. Rank is the highest logical unit and is typically used to increase the memory capacity of your system.
Say you need 16Gb of memory. Depending on what's available in the market and what is cheaper, you could have a single 16Gb memory die, in this case you would call it a Single Rank system because you just need 1 ChipSelect signal (CS_n) to read all the contents of the memory. Or you could choose to have 2 individual 8Gb discrete devices soldered down on the PCB (because 2x8Gb devices happen to be cheaper than 1x16Gb). In this case the 2 devices will be connected to the same address and data busses, but you will need 2 ChipSelects to separately address each device. Since you need two ChipSelects, this setup is called Dual-Rank.
[Side Note: One other DRAM variety you may come across is a "Dual-Die Package" or DDP. In this case you'll have a single DRAM chip soldered on the board but internally within the package it'll have a stack of 2 dies. Each die will once again share address and data lines but will have separate chip selects, making it a Dual Rank device.]
Another example - Say you need an 8Gb memory and the interface to your chip is x8. Then you could pick a single 8Gb x8 device or two 8Gb x4 devices and connect them in a "width cascaded" fashion on the PCB. With width cascading, both DRAMs are connected to the same ChipSelects, Address and Command bus, but use different portions of the data bus (DQ & DQS). In the picture below, the first x4 DRAM is connected to DQ[3:0] and the second on to DQ[7:4].
I'm constantly referring to something called "commands" -
WRITE command. But in the very first picture of this article, there is no "Command" input to the DRAM. So how are these commands issued?
Well, the DRAM interprets the
ACT_n, RAS_n, CAS_n & WE_n inputs as commands based on the truth table below.
|Refresh||REF||L||H||L||L||H||H or L|
|Single Bank Precharge||PRE||L||H||L||H||L||L|
|Bank Activate||ACT||L||L||Row Address|
|Write with Auto-Precharge||WRA||L||H||H||L||L||H|
|Read with Auto-Precharge||RDA||L||H||H||L||H||H|
The table above is only a subset of commands you can issue to the DRAM. The entire DDR4 command truth table is specified in section 4.1 of the JEDEC spec JESD79-4B.
Figure 8 shows the timing diagram of a
READ operation with burst length of 8
ACTcommand. The value on the address bus at this time indicates the row address.
RDA(Read with Auto-Precharge) is issued. The value on the address bus during at this time is the column address.
PRECHARGEsthe bank after the read is complete
Figure 9 shows the timing diagram of a
WRITEcommands are issued. The first one to address
COLand second one to
ACTbefore it because the row we intend to write to is already active in the Sense Amps
WR, so this leaves the row active. The second command is a
WRAwhich de-activates the row after the write completes.
[Side Note: I sneaked something in here without much explanation. A16, A15 & A14 are not the only address bits with dual function. The auto precharge command is issued via A10, and select BurstChop4 (BC4) or BurstLength8 (BL8) mode is selected via A12, if enabled in the mode register.]
Now that we've had a sufficiently long discussion about the DRAM, it is time to talk about what the ASIC or FPGA needs in-order to talk to the DRAM. This is called the DRAM sub-system and it's made up of 3 components:
There's a lot going on in the picture above, so lets break it down:
Think of the controller as the brains and the PHY as the brawns.
Let's wrap this up
x4, x8 or x16based on the width of the